Journal of Advanced Computing, CommunicatiOn &
Volume 5 - Issue 1
Volume 5 - Issue 1
1. OPTIMIZATION ALGORITHM USING MANET APPLICATIONS IN WIRELESS COMMUNICATION SYSTEM-(ACCT-18)Arunachalam.G, SalmaBegam.S, Deepika.R
Abstract- Mobile Ad Hoc Network (MANET) is a collection of two or more devices or nodes or terminals with wireless communications and networking capability that communicate with each other without the aid of any centralized administrator also the wireless nodes that can dynamically form a network to exchange information without using any existing fixed network infrastructure. In Mobile Ad Hoc Network (MANET), various routing protocols are there like AODV, DSDV, TORA, DSR etc. Various optimization techniques can be used to find out the best and optimal solution. Nature inspired algorithms are meta heuristics that mimics the nature for solving optimization problems opening a new era in computation.
2. AN EFFICIENT MULTIPLIER-LESS DWT ARCHITECTURE FOR IMAGE ANALYSIS-(ACCT-18)Raja Krishnamoorthy, Puvirajan Thirumurugan
Abstract- The lifting scheme is attractive for both high throughput and low-power VLSI applications. It is a spatial domain technique. In general, it has three steps: split, predict and update. The discrete wavelet transform (DWT) has gained wide spread acceptance in signal coding, data compression, data interpretation, data hiding, geophysics, meteorology, audio signal processing, motion tracking, machine learning and so on. They are especially suitable for applications where scalability and tolerable degradations are important. In this project, an efficient Multiplier less predict and update architecture for lifting based DWT is proposed. The proposed design reduces the complexity in Multiplier based lifting architecture. Even though, convolution based architecture is less efficient in area requirement, compared to conventional lifting based method. Our project presents a Multiplier less structure which is better when compared to conventional convolution and lifting based DWT architecture. The design reduces the power, number of transistors and critical path. The proposed design incorporates a pipelining architecture by which the speed can be improved. The predict and update blocks are implemented using adder and shifter for the proposed method. The proposed method is described using Quartus II 9.1 software. The proposed circuit improves power by 56%.
3. AN EFFICIENT VLSI ARCHITECTURE for PROCESSING ELEMENTS in FIR INTERPOLATION FILTER-(ACCT-18)Raja Krishnamoorthy, Puvirajan Thirumurugan
Abstract-This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multi-standard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample in comparison with individual implementation of each standard’s filter while designing a root-raised-cosine finite-impulse response filter for multi-standard DUC for three different standards. In the next step, a 2-bit binary common sub expression (BCS)-based BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This technique has succeeded in reducing the area and power usage, along with improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and can be considered more appropriate for designing the multi-standard DUC.