Journal of Advanced Computing, Communication and Technologies

JACCT

Volume 4 - Issue 2

Volume 4 - Issue 2

 

  1. A Survey On Video Coding For H.264 Using FPGA.

PRIYA.S and KOKILA.S

ABSTRACT:  Video coding using FPGA plays a major role in the present day scenario. The low power requirement and area efficiency plays a major role in VLSI. Very large Scale Integration plays an important role, integrating the entire active and passive element in a single chip with matching low power requirement, area efficiency and speed. This paper gives a review of different papers. It would be useful for the researches, for comparing various video encoding techniques. In this paper, we have compared the power, memory, gate count and throughput of four different papers.

  1. High-performance and energy-efficient 256-bit CMOS Priority Encoder

THARANI PRIYA.S and GNANA MURGAN.S

ABSTRACT: A high speed performance and efficient energy 256-bit CMOS priority encoder and realized on transistor level using 32 nm predictive technologies. The new circuit is designed with a full custom approach and incorporates 2 novel logic styles: the Multiple-Output Monotonic CMOS (M2CMOS) and the Dynamic Inversion technique (DI). The achieved performance is in the order of O(log2(N)), It are response to the input size. A simulation-based comparative analysis concludes that, compared to the conventional design, the proposed circuit achieves up to 57% improvement in delay, 8% improvement in energy consumption and 39% improvement in EDP, while maintaining 20% smaller transistor count.

 

  1. Design Of Approximate Multipliers For Area And Efficient Power

Suganthi.R and Thiruppathi.M

ABSTRACT: Power consumption is the important parameter in       VLSI circuits. To reduce the power consumption of the circuit many methods are proposed in the past. The channel length modification is the important measure. A CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low power dissipation is presented. This design is planned to be proposed in Sigma-delta ADC. This circuit combines the good features of the resistive dividing comparator and the differential current sensing comparator. The design has been carried out in Tanner EDA tools, the schematic simulation is done using Schematic Editor (S-Edit) and layout simulation of the design is verified using Layout Editor (L-Edit) using 0.25µm CMOS technology. The Simulation results are verified with supply voltages of 1.6V, 1.8V and 2.0V respectively. It is found that the power is least dissipated in 1.6V which is 0.7899 mW, but it has the longest propagation delay of 0.715 ns. In contrast, the 2.0V supply produced 1.471 mW and a shorter delay of 0.550 ns.

  1. Implementation Of High Speed Approximate Adder For Effective Area & Low Power

Gowri Manohari.R and Hemalatha.M

ABSTRACT: In most digital signal processing (DSP) applications like image processing and speech processing, human beings can collect useful information from slightly inexact outputs. Approximate circuits consume less power, require less number of transistors and have less propagation delay than exact circuits. Approximate adder is the building block of inexact computing for DSP applications. This paper presents a design of a 32-Bit approximate adder which has low power consumption and requires less number of transistors than existing approximate adders. The proposed approximate adder has power savings of 8% for 32 -Bit as compared to existing designs. The proposed adder has significant reduction in area (number of transistors) than existing designs.

  1. Real Time Of Video Stabilization Using FPGA

Monisha.V and Kokila.S

ABSTRACT: Digital video stabilization is an important video enhancement technology which aims to remove unwanted camera vibrations from video sequences. Trading off between stabilization performance and real-time hardware implementation feasibility, this paper presents a feature-based full-frame video stabilization method and a novel complete fully pipelined architectural design to implement it on Field-Programmable Gate Array (FPGA). Using pipelining and parallel processing strategies, the whole process has been designed using a novel complete fully pipelined architecture and implemented on Altera’s Cyclone III FPGA to build a real-time stabilization system. Experimental results have shown that the proposed system can deal with standard PAL video input including arbitrate translation and rotation and can produce full-frame stabilized output providing a better viewing experience at 22.37 milliseconds per frame, thus achieving real-time processing performance.

  1. Low Pass Filter Using ECG Detection For OTA-C

Vijayalakshmi.A, Jayasimha.T

ABSTRACT: This paper Design Gm-c fourth order Butterworth filter for low pass filter for ECG detection. The filter strongly depends on basic building block such as transconductance cell, low power, highly linear. Pseudo differential transconductance cell working at 0.5 V in 180nm and n well CMOS technology. The gain of transconductance cell 57 db .Power consumption is 15 nw. The low pass filter with pass band gain 0 db. Cut off frequency 250Hz.Total power consumption is 157.5nW. The design implemented in TANNER TOOL 13.1 version to obtain the waveform.

  1. Design of A Low Power Comparator Using Domino Logic

Gowri.P and Ravikumar.G

ABSTRACT: The implementation of 4 bit comparator circuit using Domino Logic (High speed Domino) and CMOS Logic. The CMOS Logic during inverter circuit operation when voltage level shifts from high to low and vice versa short circuit current occurs which leads to power loss. So this is one of the power saving technique which helps to avoid this short circuit current and saves power consumption. So we have made a comparative analysis between the Domino logic and the CMOS logic for which we have used comparator as our reference circuit. The parameter which we have considered in this paper is power. We also tried to fetch power consumption at different voltage level (voltage scaling) and at least 55% of power is saved by Domino Logic as compared to that of CMOS circuits. In this paper 0.25µm technology is used. And LTSPICE is used to implement the circuit for simulation result.

 

  1. Design Of Approximate Multipliers For Area And Efficient Power

Anish Girija.G and Dr.Senthil Kumar.V.M

ABSTRACT:  The design complexity with an increase in performance and power efficiency for error resilient applications can decrease approximate computing. This approach for an approximation of multipliers deals with recent design. To begin of changing probability terms in the design the partial products of the approximate multiplier are also changed. Based on their probability logic complexity the approximation is varied for the accumulation of altered partial products. The proposed multiplier is designed in two variants of 16-bit multipliers. Synthesis results shows that the two designed multipliers produces power savings of about 72% and 38% when it is  compared to an existing multiplier. When compared to existing approximate multiplier they have better precision and the Mean relative error figures are as low as 7.6% and 0.02% for the proposed approximate multipliers which are better than the earlier works. Performance of the proposed multipliers is evaluated in an image processing application, thus one of the planned models achieves the maximum peak signal to noise ratio.

  1. A Survey Design And Implementation Of A Cloud-Based IoT Scheme For Precision Agriculture

Ranjitha.S.N, Shanmugavalli.V and Dinesh Kumar.R.T

ABSTRACT:  The Internet of Things (IoT) technology is currently shaping different aspects of human life. We are designing, building, and evaluating a system for precision agriculture which provides farmers with useful data about the soil, the water supply, and the general condition of their fields in a user friendly, easily accessible manner. Our system aims to make cultivation and irrigation more efficient as the farmer is able to make better informed decisions and thus save time and resources. The diversity of location and climatic effects upon agricultural cultivation, along with other environmental parameters over time makes the farmer’s decision-making process more complicated and requires additional empirical knowledge. Applying wireless sensor networks for monitoring environmental parameters and combining this information with a user-customized web service may enable farmers to exploit their knowledge in an efficient way in order to extract the best results from their agricultural cultivation. The system can scale based on each farmer’s demands and the resulting ensemble of collected information may represent a valuable resource for future use, in addition to its use for real-time decision making. The design of the precision agriculture system contains a prototype solution regarding the sensor platform and a customizable service that can be utilized in different ways and by several entities. The proposed three-layer architecture collects the needed data and relays it to a cloud-based back-end where it is processed and analyzed. Feedback actions based on the analyzed data can be sent back to the front-end nodes. We built a prototype of the proposed architecture to demonstrate its performance advantages.