Journal of Advanced Computing, Communication and Technologies


Journal of Advanced Computing, CommunicatiOn &


A Novel Circuit Methodology to Improve the Transition Delay and Provide Signal Feed Through For Input Data in Pulse Triggered Flip Flop


In this work, a new method to improve the transition delay, Conditional Pulse enhancement and reduction in transistor count for Flip Flop is proposed which consumes less power and area. The design featuring an explicit type pulse-triggered structure improves the problem arises due to transition delay. The clocked Pseudo NMOS style structure enhances the efficiency and reduces the load capacitance. The design which successfully solves the long discharging path problem also reduces the transistor count in the discharge path. The Proposed circuit is implemented using Predictive technology Model in CMOS 90-nm technology. The proposed design outperforms the existing method by reducing the power by 15% and 40% with two existing methods.

Index Terms— Flip-flop (FF), low power, pulse-triggered, Transition Delay, Conditional Pulse enhancement.

  I. Introduction

Memory Devices are getting developed day by day in different applications. New technology has allowed the chip to be so small and to consume less power. In literature several methods are available which improves the design and consume lesser power Background Methodology.
Pulse triggered Flip Flop are of implicit and explicit type.  The two types of P-FF face one important problem. The transistors of pulse generators used in the P-FF normally vary in their W/L ratio and are often enlarged. So it can generate pulses of wider ON period to trigger the data capturing of the latch.

Figure 1. P-FF Design with Pulse Control Scheme

                                                                                                                                                          I. Proposed P-FF Design

In this work a low-power flip-flop (FF) design is proposed (Figure 3) featuring an explicit type pulse-triggered structure based on conditional pulse enhancement and signal feed-through scheme. The proposed design distinct from the previous two methods proposed separately for delay reduction and power reduction. Three important problems are available in the existing circuits of the P-FF, first charge deficiency at nodes, more number of transistors in the discharging path and third one is the delay constraint.  The proposed design with three structures in the circuit overcomes the problems associated with existing P-FF designs. The first one is a pseudo-nMOS logic style structure is designed using a weak pull-up pMOS transistor P1 with gate connected to the ground. P1 keeps the charge in the internal node connecting between the first stage and second stage. The load capacitance is also reduced by this method. Secondly the number of transistors stacked in the discharge path is reduced. Thirdly a pass transistor N5 is controlled by a pulse clock which enables the input data to drive the output node of the latch directly. The N5 along with P2 reduces the delay in transition by allowing a extra passage facility.  N5 loading effect is negligible since it turns ON for a very less time.